As planar bulk MOS (Metal Oxide Semiconductor) devices are known to reach the scaling limits, fin field effect transistors (FinFETs) or Trigate FETs have become popular in recent days as a technology option for sub 20 nm node gate lengths. Moreover, FinFETs may be a suitable option for System on Chip (SoC) application, which may be indeed a key requirement for reduced cost, size and power while enjoying better performance in the technologies below the 20 nm node. A SoC chip in advanced CMOS (Complementary Metal Oxide Semiconductor) may commonly consist of various blocks including robust electrostatic discharge (ESD) protection. Current ballasting may be used to achieve uniform conduction in the fragile fins.
SCRs (Semiconductor Controlled Rectifiers) in advanced CMOS are among those devices, which may be used for a robust ESD protection. It may be desirable to apply current ballasting techniques with SCR devices for, e.g., bulk FinFET technologies in order to achieve, e.g., efficient and robust ESD protection capabilities.